News Archive

DARPA Funds SDSC to Investigate Tera Multithreaded Computer Architecture

Published 08/04/1997

For more information, contact:
Ann Redelfs
San Diego Supercomputer Center
619-534-5032 (voice)
619-534-5077 (fax)

The University of California, San Diego (UCSD) has received a $1.9 million, 18-month award from the Defense Advanced Research Projects Agency (DARPA) to implement, optimize, and evaluate defense-related applications on a new kind of supercomputer, the Tera MTA. UCSD and the San Diego Supercomputer Center (SDSC) will lead a multi-partner research team that includes The Boeing Company, the California Institute of Technology (Caltech), Jet Propulsion Laboratory (JPL), Sanders (a Lockheed Martin Company), the Naval Command, Control and Ocean Surveillance Center, and Tera Computer Company.

The Tera MTA (for Multithreaded Architecture) uses a radical new machine architecture that could revolutionize high performance computing. Each processor supports up to 128 threads of execution, allowing much higher processor use than in traditional architectures. Moreover, multithreading extends naturally to multiple processors and so increases the possibility of approaching perfect speedup in which performance scales up linearly as more processors are added. Finally, the MTA has shared memory, which leads to a more convenient programming model than that for parallel (multiple processor) computers that have distributed memory.

"This newly funded project should determine whether multithreaded architectures will allow major defense applications to scale up to sustained multi-gigaflops performance," said Wayne Pfeiffer, principal investigator for the project and deputy director at SDSC. "Some of these applications perform poorly or do not scale on conventional parallel computers, even after extensive reprogramming. If successful, this project will enable simulations at unprecedented resolution and allow more responsive command and control operations."

Until now, studies of multithreaded architectures have had to rely primarily on simulators and models, which are difficult or impractical to apply to large-scale applications. The DARPA project will allow researchers to perform experiments on an operational multithreaded computer, the first Tera MTA, which will be delivered to SDSC later this year through a grant from the National Science Foundation. Investigation of the Tera MTA's suitability for complex, defense-related applications will substantially extend the NSF-funded initial evaluation of the MTA running academic applications.

Earlier this year a Tera MTA prototype recorded the fastest single processor performance ever for integer sorting. On the NASA NAS Parallel Integer Sort benchmark, the MTA ran 1.31 times faster than a Silicon Graphics CRAY T90, the previous record holder. "Further improvements are expected, since the prototype isn't as fast as the multiprocessor system we will be delivering to SDSC," said Jim Rottsolk, Tera Computer Company's president and chief executive officer.

"We're looking forward to working with this machine," said Robert Dukelow, head of the Processing Technology Branch at the Naval Command, Control and Ocean Surveillance Center's Research, Development, Test and Evaluation Division (NRaD) in San Diego. NRaD will attempt to adapt sonar algorithms for long range detection, classification, and tracking of underwater vehicles to the Tera MTA. NRaD engineers will explore the potential of the MTA to execute acoustic processing algorithms in a dynamic, real-time operating environment. "Cost of software development is a major concern to DoD, and developing complex software for the current generation of parallel computers is very expensive," he said. "If the MTA lives up to its promise, this project may lead the way to lower-cost, higher-performance computation for very demanding applications in such areas as real-time sensor processing, data fusion, command and control, and high-resolution simulations."

Tera will work with the partners to design, optimize, and evaluate the performance of several major defense applications and will assume primary responsibility for a computational fluid dynamics application, TRANAIR, that is heavily used at Boeing. Tera will determine whether this CFD application is best suited to the Tera MTA and whether algorithmic changes are needed to obtain superior performance.

Boeing will study an electromagnetics application that has been investigated for parallelism on shared-memory and distributed-memory platforms, and is running on both parallel systems and PC/workstation clusters. This application currently is being evaluated to see if scalable library technology being developed under a separate DARPA contract will provide algorithms that can take better advantage of newer architectures.

Caltech and its associated JPL will study two parallel applications on the Tera MTA: a synthetic theater-of-war simulation and a command, control, communication, and intelligence (C3I) application. The SF Express Project is exploring the use of scalable parallel computers to conduct simulations of synthetic forces of 50,000 vehicles or more, using a parallelized version of the ModSAF code developed under DARPA funding by Caltech, JPL, and NRaD. The Multithreaded C3I Applications Project will develop multithreaded implementations of three or more applications from the C3IPBS parallel benchmark suite developed for Rome Air Force Laboratory by Honeywell.

Sanders, a Lockheed Martin company, will implement a real-time, high-resolution synthetic aperture radar application that now runs on Sanders' own embedded computer systems. Sanders also will evaluate the Tera MTA as a real-time engine for embedded systems. Sanders currently builds some of the most demanding embedded systems in the world, requiring hundreds of processors. Multithreaded architectures provide an innovative way to obtain more performance from a processor by ensuring that the processor is never idle.

In addition to applications-oriented studies, related investigations will be done by researchers in the Computer Science and Engineering (CSE) department at UCSD. According to Larry Carter, professor of CSE and SDSC Senior Fellow, "We will explore new compiler and code generation techniques that automatically produce the large number of threads needed to keep multithreaded architectures fully utilized. We will explore how an application can adapt itself as it is running to take advantage of changing runtime conditions or its changing execution profile, and we will consider the even larger question of how the scheduler can find a mix of applications that will share multiple types of resources rather than competing for one."

SDSC, a national laboratory for computational science and engineering, is affiliated with the University of California at San Diego, administered by General Atomics, and sponsored by the National Science Foundation, other federal agencies, the State and University of California, and private organizations. For additional information about SDSC, see, or contact Ann Redelfs, SDSC, 619-534-5032, .

Tera Computer Company designs and builds high performance MTA computer systems for very large simulation and database problems. The company has its headquarters in Seattle, Washington. An account of the single-processor Tera MTA benchmark speed record is contained in Tera Computer Company's press release "Tera Announces First Quarter 1997 Results," available on the Web at For more information about Tera and MTA, refer to Tera's Web site at, or contact either Deborah Stapleton, Stapleton Communications Inc., 415-988-9207, or Dick Russell, 206-325-0800, .

The project "Evaluation of a Multithreaded Architecture for Defense Applications" (DARPA Control # 9703509) is sponsored by the Defense Advanced Projects Research Agency, is issued by the Directorate of Contracting, ATZS-DKO-I, Ft. Huachuca, AZ, and is administered by ONRRO, San Diego, CA. The content of the information in this press release does not necessarily reflect the position or the policy of the Government, and no official endorsement should be inferred.