Trip Report
Intel Supercomputer Users Group (ISUG) '95
June 21-24, 1995
Albuquerque, New Mexico
The next ISUG is in Knoxville TN (hosted by ORNL) from June 19-22, 1996.
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Ed Masi,
General Manager Scalable Systems Division, Vice President Intel
"Charting a New Course for the High Performance Computing Industry"
Ed mentioned that at a recent meeting (a jamboree) that Intel SSD sought the advice and direction from two of its most highly regarded customers, Mr. Paul Messina of Caltech and Sid Karin. He went on to say that he has high confidence in the direction which Intel is moving.
Ed showed several foils which were used three or four years ago. The slides described Intel's analysis of the supercomputer field at that time:
The supercomputer industry as a whole was to decline further
The commercial market was a lucrative direction
No existing MPPs on the market were effective
Strategy:
- Focus on SHPC
- Work with strategic partners
- Deploy Paragon technology as a building block
He went on to point out that Intel's predictions, for the most part, came true.
Ed also mentioned that ongoing collaborations with Oracle and Unisys are of great importance to Intel SSD.
Some interesting quotes/paraphrases:
Intel is driven by doubling performance every 18 months.
The motherboard is the building block, not the microprocessor.
Intel SSD's focus is to compete directly with IBM by providing a bottom to top product line.
The P6 will be the microprocessor used on future SSD products.
NT will win in the long run. It's not a matter of whether, but when.
Ed also described what he believes will be a strong factor in the future of Unix. He mentioned that as vendors are faced with porting their own Unix operating systems to new and upcoming 64 bit architectures that the likelihood of NT becoming the OS of choice grows better. I believe he quoted 80 million dollars as the cost to port and maintain a Unix operating system. He suggested that providing NT will be much more inexpensive for hardware vendors.
Bob Voight,
National Science Foundation
"The HPCC Program: Past, Present, and Future (?)"
The question mark in Bob's title set the tone for the talk. Bob referred
to a web page
http://www.hpcc.gov
to see the on-line "Blue Book" document.
He described the Supercomputer Center Task Force which is currently underway to make recommendations for the future of the NSF Centers. The task force is headed by Edward F. Hayes of Ohio State (ehayes@osu.edu). Bob mentioned that anyone in the audience who wanted to provide feedback to Ed Hayes should certainly send him e-mail. Apparently the task force's report is due in the October '95 time frame. The alternatives being considered include:
1) N <= 4 Centers. Effectively, business as usual with maybe fewer sites.
2) N < 4 Centers. The remaining centers would establish formal
partnerships with non-NSF centers, hooked via
high-speed networks. This sounded like remaining
centers would be expected to maintain regional
affiliate relationships.
3) N = 1 center. The remaining Center would be the "leadership center"
for the NSF.
4) N < 4 centers. The remaining centers would each be "disciplinary
centers" with different focuses.
5) N = 0 centers. No centers would be supported.
An on-line survey may be obtained at the web address:
http://tf-survey.osc.edu/
Paul Messina,
Caltech
"The Scalable I/O Initiative -- Initial Activities"
Paul explained that he has been working on this project for three years and finally just last month won funding for a part of it. With the new funding he plans to procure some equipment (a 90-node Paragon with multiple disk peripherals) and also increase efforts on software and design work.
He also mentioned that Caltech and Argonne are the two primary contributors on the project.
I was surprised to hear of Caltech's plans to acquire an archival storage system based on HPSS. I was not aware of this.
Mike Bailey
San Diego Supercomputer Center
"Parallel Photorealistic Rendering"
Mike then described the Renderman efforts at SDSC. Mike's presentation (and use of well known examples such as clips from Beauty and the Beast, Terminator, etc.) and collaboration with Pixar was very well received. It was an impressive display of commercial use of the Paragon, and innovative programming to schedule the rendering across multiple nodes.
David Follett,
GigaNet Inc.
GigaNet has built a new ATM interface specifically for the Paragon. By contractual agreement the interface will provide 275 Mb/sec TCP/IP performance and will be available by 3Q95. David stressed however that the actually performance will far exceed 275 Mb/sec.
David brought up some interesting points. And, later discussion with David and others (someone from NetStar for example) proved interesting. It would appear the GigaNet will be able to provide extremely fast ATM I/O to and from the Paragon. But it is unclear whether any ATM switches in the market today will be able to support such bandwidth. So early users of the ATM devices may choose to use them point-to-point (directly attached to two supercomputers).
I spoke to David following the presentation and discussed the possibility of SDSC beta testing an interface during SC'95. He expressed interest but suggested that this be coordinated with Intel. He believes that they will have very few available devices available in the next few quarters.
Refer to the "Planning for SC'95 Demos" section for more details on a
proposed use of an ATM interface for the Paragon.
Larry Meadows,
Portland Group Inc.
"The Intel Paragon HPF Compiler"
Doug Miles from PGI (Portland Group Inc.) was supposed to give a presentation on HPF but instead Larry Meadows of PGI gave one. There was no information which was new to me. PGI's HPF compiler will (in some cases already is) F90 compliant. None of their compilers are fully HPF compliant yet.
Mike Wall
Director of the Intel Supercomputer Business Unit
"Intel Supercomputer Business Update"
Mike started by discussing SDSC's success with the Paragon. He stated that at SDSC the throughput on the Paragon has exceeded the throughput of our C-98 (quoting 2.4 GFlops).
He also referred to SSD's four largest (known) customers:
Oak Ridge National Lab 3072 MP nodes
Sandia 3744 GP nodes
Caltech 1024 GP nodes
SDSC 800 GP nodes
Peter Wolochow,
Director of Intel Supercomputer Product Marketing
Peter made a very interesting comment. He mentioned that at the time when the Intel Pentium chip was experiencing floating point errors, Intel was flooded with calls from customers. It was by such contact that Intel had realized how strong and widespread the scientific computing market was... and that their microprocessor was being used for this purpose.
Ken Kliewer,
ORNL
"Innovation in a Production Envrionment"
Ken mentioned that ORNL has a web address which provides info about a number of software packages including MPI, HPF, FORGE, C++, and the NSL UniTree commands uti() and wuftp(). The web address is http://www.ccs.ornl.gov
The uti command allows piped input/output to UniTree so, for example, an administrator can dump and/or restore directly to UniTree.
Security Panel:
A General Session Discussion
A Paragon security panel discussion was held in one of the general sessions. The panelists were Buddy Bland, ORNL, George Kremenek of SDSC, Kevin McCurley of Sandia, and several people from Caltech. Interestinly, all members except Sandia currently rely on unencrypted passwords traversing the Internet. Sandia has employed a firewall mechanism around all of their systems. It was agreed that firewalls reduce usability of the systems. George described SDSC's current configuration and explained our current plans and concerns.
The discussionwas very well received and continued past its scheduled time. There was a lot of good information disseminated, and a lot of questions asked. I was pleased to see the discussion follow the security concerns originally raised by SDSC and ORNL several months ago (which resulted in the scheduling of the security panel discussion).
Intel has (finally) assigned the issue of security to someone. Shane Story
(shane@ssd.intel.com) is the Intel point of contact for security issues.
Security Issues:
Over the course of the conference Shane and I met a number of times and discussed various security topics.
The following was clearly communicated to him:
Intel needs to track securty problems in their PTS database. Currently they have no method to track any security problems, past or present.
Intel must begin to track CERT/CIAC advisories, including advirories from years gone by.
Intel should consider porting Kerberos to Paragon OS. Shane and I talked in detail about possible SDSC/Intel collaborations on this topic.
Intel should consder the benefits of collaborating on security related software development and research.
Shane and I plan to discuss these issues more in the coming weeks.
Other sessions/seminars/tutorials attended:
A discussion on a scalable partitioner for unstructured finite element meshes.
An evaluation of the Paragon on active message communication.
A discussion on how Intel temporarily (for two days) connected as many nodes as possible resulting in a 3000+ node MP system. On this system they ran LINPACK and achieved 281 GFlops sustained. They stressed the ease in which the system could be scaled.
A customers evaluation of High Performance Fortran (NOT PGI)
A presentation from Chris Wood of Maximum Strategy on client/server data serving for high performance computing.
Several talks on shared virtual memory environments.
A description of the PUMA operating system.
A comparison of Paragon OS to SUNMOS performance.
Planning for SC'95 Demos:
I spoke at length with Joanna Lees (in charge of SC'95 demos) and Bob Wallace (in charge of SC'95 coordination... and card trick extrodinare). Mahesh Rajan (Intel's applications analyst located, at SDSC) was very helpful in arranging the meeting. We discussed a number of possibilities for joint demo efforts. These included:
GLMS - distributed between an alpha workstation, an SDSC Paragon and Intel's Paragon at the convention center.
Ocean/Atmospheric demo using SDSC, Caltech, and/or Intel's Paragon at the convention center.
We discussed the issue of acquiring an ATM interface for an SDSC Paragon for use in a demo.
We discussed Kim Baldridge and Jerry Greenberg's participation in a joint demo.
Jeff Mandell's code.
Intel would like several (at least one) pictures for use in their booth. The image should be in electronic format (one high-res, one low res for use in web page). Also, a short write-up should be supplied by SDSC on each image. Intel will then blow up the image (several feet squared) and mount the picture in their booth.
Intel also plans to put together several workstations which run netscape at SC'95. They intend to have participants sit down in front of monitors and to browse through the web pages. They will be interested to get web info from SDSC for inclusion in their "web page demo" exhibits.