Some things to keep in mind are:
Use hierarchical design (subcircuits) to make your design easier to understand and think about. The highest level schematic should be mostly functional elements (registers, alu, memory, etc.) and wires/buses.
Isolate control. Follow the text's lead by generating all control signals in one place
from the opcode. This should make the design easier.
You will create a ROM to hold instruction memory and a RAM to hold data memory. Both will be initialized-the ROM(s) to hold your programs, the RAM to hold your input data. Instructions to create memory parts in Xilinx are on the web page.
You should have 1 ROM and just initialize 4 different values of the PC.
You should have an init signal to set the PC to the start of the program(s). This signal
can initialize data memory locations as well.
Please have a DONE signal that goes high at the end of the program (insert a halt instruction).
I want you to have a cycle counter that we will use to reliably determine dynamic instruction
count. It should start at 0 and count until the DONE signal goes high.
Keep in mind that you will (probably) have to debug your programs. Think about how to make your life easier before this happens.
Remember that it is YOUR responsibility to convince us your CPU works, not ours to figure out on our own. Provide clear and sufficient results to back up the fact that your design works.
What to turn in:
A review of the ISA
Schematics of all circuits (including Lab 2), hierarchically organized. The highest level design must have all the signals necessary to demonstrate correct program execution via the timeing diagram.
A timing diagram for each program demonstrating correct operation and other important data. At minimum show results being generated, the cycle counter, the PC. You do not need to show the whole program (especially if it takes 100's of cycles!), but
certainly show the beginning and end and some execution of main loop(s).
Annotate heavily to show what is going on!
Assembly and machine code of all main programs.
Answers to following questions:
1) Did you have to modify your ISA? If so, how and why?
2) What is the dynamic instruction count of programs 1, 2 and 3 and 4?
3) What could you have done differently to reduce dynamic instruction count?
4) How hard was your design? Could you have made it easier (knowing what you know now)?
5) How easy or hard would it be to extend your design to a multi-cycle design and/or
a pipelined design? Give examples.
6) What would you do differently if the goal was ease of programming rather than dynamic instruction count or ease of design?
7) What instruction takes the longest in your design? If this is a multi-cycle instruction, what single-cycle instruction takes the longest (and thus determines the cycle time?)
8) What could you do differently to reduce cycle time?
Grading:
The grade for lab3 will be partially based on the documentation above and
partly on live demonstration of your design in lab. Shortly we will begin
a schedule for demonstrations. You will need to sign up in advance for
a 30 minute slot to schedule your demonstration.
Groups of no more than 3 persons can turn in a lab report together.
You can switch groups now from Lab 2 but ONLY IF YOU TELL ME.