CSE 141L Lab2. 8-bit ISA. Due Monday Oct. 24th

In this lab assignment, you will design the ALU (arithmetic logic unit) and the internal storage of your CPU, connect them together, and demonstrate that they work together through schematic and timing printouts. The internal storage means the registers, stack, or accumulators (depending on your ISA) not main memory (RAM). Presumably even a machine without explicit loads and stores (such as a stack machine) has somewhere local (default) to store arguments for such things as adds and muliplies. You need to design those.

The internal storage (we'll call it the register file from now on), should be connected to the ALU similar to the sample schematic. In the sample, the ALU has 2 8-bit inputs, an 8-bit output, and 3 control signal bits. The register file has 1 8 bit input, 2 8-bit outputs, various control signals (to get it to read and write for example). The SRCA (Read Reg Address A) signals are the address of the first source register, the SRCB the addresses of the second source register, and DEST (Reg Write Address) the address of the destination register. The multiplexor allows me to initialize the registers to demonstrate the operation of the circuit since it is not wired up to program memory and can't actually execute a program (yet). You have to come up with a similar kludge to get values toggled in to your operands and run the circuit to write output.

You will demonstrate your design in two ways. First, you must come up with a schematic such as the one shown. Obviously yours will be different as it must implement the ISA you designed in Lab 1. You must show all the relevant internal circuits. Second, you must have a timing diagram for all of the ALU operations supported by your design. There is an example timing diagram included; yours will be longer to cover all of the operatrions in your ISA/ALU. The timing diagram has to demonstrate all ALU operations with interesting inputs (try some from your programs in Lab 1). The timing diagram should also demonstrate and exercise the register file - causing values to be read and written. If you hav general purpose registers (that can be 1st or 2nd operand, or source and destination) then I want to see those features exercised.

Just like in real life, the quality of your presentation counts. The schematics and timing digrams must be complete and heavily labled and annotated so that we can figure out what is going on! An elegant solution that is poorly documented will not recieve full credit.

In addition to the schematics and timing, answer the following questions:

  • 1. Summarize your ISA from Lab 1. Indicate where each instruction is demonstrated.
  • 2. How many (and what) ALU operations do you support?
  • 3. Will your ALU be used for non-arithmetic instruction (e.g., address calculation, branches)? If not, how are these things calculated? If so, how does that complicate the design?
  • 4. Do any of your instructions use the ALU more than once (take multiple cycle)? Or do any of your instructions need 2 ALUs (or more) to get a complicated instruction done on 1 cycle?
  • 5. Where do your ALU control signals come from? Are they directly coded into your opcodes? If not, how much translation circuitry is needed? Now that you see how opcodes imply hardware, is there anything you would do differently in the design of your ISA to reduce ALU design complexity?
  • 6. Now that the ALU is done, are there useful instructions you could think of that would be easy to add?
  • 7. Is there anything you would redo in your ISA design to make the register file (or whatever you are calling it) design easier?

    Groups of no more than 3 persons can turn in a lab report together. You can switch groups now from Lab 1 but ONLY IF YOU TELL ME.