Your instruction set architecture should feature fixed-length 8 bit instructions. You need to describe:
what operations your ISA supports and what the OPCODES are.
how many instruction formats your ISA supports and what they are (in detail) -- how many bits for each field, where these fields are found in the instruction (remember the whole thing is only 8 bits long!). Your instruction format description needs to be as detailed and specific as the MIPS descriptions
given in the text (for example in figure 3.25). Your description
must be detailed enough that someone could write an assembler for it (see
section 3.9).
number of registers -- general-purpose or specialized.
the size of main data memory in bytes (1 byte = 8 bits!)
the addressing modes supported (for both operations that take arguments
from memory and for branch instructions).
In order to fit all this in only 8 bits, the memory demands of the programs will have to be small. For example, you will have to be clever to have a conventional main memory even as big as 256 (2^8). However, for the programs you are
going to run you may not need all that much memory. You should determine how much data space you are going to need before you finalize your instruction format since it takes bits to encode memory addresses. You can assume that instructions come from a separate instruction memory (this is actually not uncommon on real processors) so your data addresses just have to be big enough to hold
your data. You should also notice that these programs probably do not need procedure calls and stack pointers. Since this is an 8 bit machine, memory is byte (8 bit) addressable. Every byte needs its own address. Registers are also only 8 bits.
When implemented, this will be a single cycle machine (no pipelining). Each
instruction takes 1 cycle and no more. You should assume that there is a
limit to what an instruction can do in 1 cycle. So, for example, you cannot
reasonably have 1 single instruction that executes one of the entire programs
below! (But it is a good idea to consider specialized instructions for the
programs below! Hint, hint - for extra credit!).
Assume that you CANNOT do two memory operations on 1 cycle. So you cannot do
2 reads of 2 arguments, or a read and a write (or 2 writes) on 1 cycle. You will have to break these up into multiple instructions.
However, you can read 2 REGISTERS and write 1 all in a single cycle. (Don't
try to do 2 register writes in a single cycle though - possible but hard.)
To simplify the ISA design process, you need to optimize only for the following goals:
Minimize dynamic instruction count (the TOTAL number of instructions executed in the program).
Simplify your processor hardware design.
These two goals may conflict! I want your lab report to describe the tradeoffs and the choices you made. You are welcome to optimize for other things (e.g., ease of pipelining, cycle time) but the two above have priority.
Generic ISAs will be frowned upon and graded down. The point of this exercize will be to optimize your design for the specific programs given below (this is similar to the real world where you might be designing a Gameboy for example.)
Groups of no more than 3 persons can turn in a lab report together. The lab report is not to exceed 8 pages. The report will answer the following questions (clarity and full description counts!).
All labs will have 2 parts: a lab REPORT (the description of your ISA) and
ANSWERS to each of the following questions. You can cite the report
in answers to the questions.
1. What instruction formats are supported and what do they look like? Give an example of each.
2. What instructions are supported and what are their opcodes?
3. How many registers are supported? Is there anything special about
these registers?
4. How many branches are supported? What is the maximum branch distance?
5. What addressing modes are supported? How are addresses calculated?
Include a description of how you calculate BRANCH addresses. Give examples.
6. How many bytes is main memory?
7. In what ways did you optimize (reduce) dynamic instruction count?
8. In what ways did you optimize ease of design?
9. If you optimized for anything else what and how? (It's o.k. if
you didn't).
10. What do you think will be the bottleneck in your design? In other words, what resources will you run out of most quickly for large, complex, programs?
11. What would you have done differently if you had 2 more bits per instruction?
12. What would you have done differently if you had 2 fewer bits per instruction?
13. Can you classify your machine in any of the classical ways (e.g. stack machine, accumulator, register, load, store)? If so, do so. If not, say why and give a new name for your machine class,
14. Give an example of an "assembly language" instruction in your machine, then translate it into machine code.
For the questions below give assembly intructions. Make sure your assembly format is either very obvious or very well described! State any assumptions you make.
15. Write a program to compute A*B. A is in memory location 0, B is in
memory location 1. Write the result (note the product of 2 8-bit quantities could require 16 bits to represent) in locations 126 and 127 . Write the result (16 bits) in locations 126 (high bits) and 127 (low bits). Since we haven't covered number systems yet, you can assume the numbers are unsigned. What is the dynamic instruction count of this program if A = 121 and B = 9?
16. Palindrome Detection. Write a program to determine if a sequence of
bytes representing uppercase letters is a palindrome. If the string is empty
(represented by the EOL marker) then the answer is trivially yes.
Let's say 0 codes to A, 1 to B, 2 to C, 3 to D, etc. and 25 to Z, 26 codes to space and 27 codes to EOL. Don't count EOL as a letter, it just tells your program when to stop scanning input. You can assume the first letter of the string to be searched in memory location 0. The string to be searched will never be longer than 100 characters (counting spaces as well).
If the sequence of bytes is a palindrome
, write a 1 in location 127. If it isn't, write a 0.
What is the dynamic instruction count on the input ABLE WAS I ERE I SAW ELBE(EOL) .
17. Write a program that determines if a list of numbers is "almost sorted".
A list of numbers is "almost sorted" if no number in the list is more than 1 position off from where it would be in a sorted list. So 1,2001,3 is "almost
sorted" since 2001 and/or 3 are only 1 position off. But 2001,1,3 is not
"almost sorted" since 2001 is 2 positions off from where it should be in the list. Assume the numbers list starts in memory location 0 and goes to location 75. If the list is "almost sorted" or in fact sorted, put a 1 in location 76.If it isn't "almost sorted", but a zero there. What is the dynamic instruction count if the list is NOT "almost sorted" and the first element that violates the "almost sorted" property is in memory location 42?
18. RNA Sequence Similarity. Write a program to detect the two closest
matches to an RNA sequence in an RNA database. An RNA sequence is a word from
the alphabet {U,C,G,A} terminated by an EOL. Your target sequence starts
in memory location 0 and will not be longer than 20 characters (including EOL).
Your target database is a set of RNA sequences delimited by EOLs. It starts
in memory location 20 and will not extend beyond memory location 110. The
end of the database is delimited by two consecutive EOLs. Two RNA sequences
get similarity scores based on how much their *initial* sequences match.
So UCGAUCGA compared to UCGAUCGA gets a score of 8 because the sequences
are exactly the same and match in every letter. UCGAUCGA and CCGAUCGA
get a score of 0 because they don't match even in the first character.
Two sequences do not have to be the same length to get scored. UCGAUCGA and
UCG gets a score of 3. Write the number of the sequence in the database that
is the best match in memory location 127. Sequences are numbered from the start of the database starting with 0. Write the number of the sequence in the database that is the second best match in memory location 126.
What is the answer for UCGAUCGA compared to UUUUEOLUCGEOLAUCEOLUCGAUCGEOL ?