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UC San Diego and SDSC to Test the First High Performance Computer Based on Novel Multi-Threaded Architecture

Published 11/11/1996

Media Contacts:
UC San Diego: Denine Hagen (619) 534-2920
San Diego Supercomputer Center: Ann Redelfs (619) 534-5032
Tera Computer Co.: Jim Rottsolk (206) 325-0800

San Diego, CA -- A revolutionary new computer architecture will get its first test run at the University of California, San Diego (UC San Diego) through a multi-year, $4.2 million National Science Foundation grant with additional funding from the state. Computer scientists across the country are hopeful that the architecture will demonstrate the technology needed for future generations of petaflops supercomputers -- computers a thousand times more powerful than the fastest computers being designed today.

Under the grant, UC San Diego will evaluate the first Multi-Threaded Architecture (MTA) computer built by Tera Computer Company of Seattle. Installed at the San Diego Supercomputer Center (SDSC), the computer will be available to researchers nationwide. Currently, a prototype Tera MTA system is undergoing tests in Seattle and has run its first programs.

"This research project underscores the great interest that the scientific community holds for the MTA," said Wayne Pfeiffer, associate director of the Center for Advanced Computational Science and Engineering at UC San Diego and principal investigator on the grant. "If proven successful, the architecture could overcome the hurdles faced by today's high-performance parallel computers -- scalability and programmability."

The cooperative agreement between UC San Diego and Tera calls for initial delivery of an MTA computer in early 1997 and covers up to eight high-speed gallium arsenide (GaAs) processors with eight gigabytes of shared memory. With additional funding the system could grow substantially.

Existing parallel supercomputers achieve high peak performance by using many processors; however, applications often fail to benefit as the systems scale up to more and more processors. Furthermore, because memory is distributed among the processors, it is harder to write applications that optimize use of the computing power.

The MTA has two key features that address the programmability and scalability issues. First, the memory is shared rather than distributed among the processors. Therefore, with sophisticated compilers developed for the MTA, programming the system will be much easier.

Second, the MTA minimizes the time that processors spend waiting by using multiple "threads"--from which the system takes its name. Because Tera compilers distribute tasks to take advantage of the threads, the MTA will be truly scalable: application performance will continue to improve as processors are added.

"Most of the big computing challenges today involve application programs that can't be distributed for higher performance," said Burton Smith, Tera's Chief Scientist and the innovator behind the MTA concept. "This makes those supercomputer architectures that rely on conventional microprocessors less and less relevant."

A thread, in essence, acts like a mini-processor. As a program runs, it is broken down into individual tasks, and each task is executed by a different thread. Each of the Tera's physical processors can handle up to 128 threads simultaneously, switching automatically from one thread, which is waiting for data to return from memory, to another thread that is ready to execute. In effect, the threads keep each processor busy almost all the time.

This mechanism for hiding the idle time, or latency, while a processor fetches data from memory is critical for achieving petaflops performance -- quadrillions of operations per second. At that speed, the time spent waiting on memory fetches can be substantial.

"Tera's latency hiding technique is a radical departure from existing machines, and we are extremely interested in seeing its realization," said Larry Carter, professor of computer science and engineering at the UC San Diego School of Engineering and co-investigator on the grant. "Our role is to test the viability of the architecture and its components, such as the compiler, operating system and networked processors, and to develop tools and methods to improve the performance where needed."

During the evaluation period, UCSD and SDSC investigators will port applications from chemistry, fluid dynamics, database management, and graphics to determine whether the system lives up to its potential. Tera is also working with independent software vendors to implement applications that are of key interest to industrial users.

"Programming is the fundamental obstacle to the wider use of high performance computers in industry," said John Van Rosendale, director of the New Technologies Program in NSF's Division of Advanced Scientific Computing. "Shared-memory multiprocessors, as exemplified by the Tera MTA, should greatly simplify this programming problem."

A number of federal agencies have expressed interest in the Tera MTA system, Van Rosendale said, since it may be able to perform important applications in many disciplines much better than existing parallel architectures. Industry uses high-performance computing for both designing products and testing prototypes, among other applications. For example, automobile manufacturers use computer simulation to reduce the weight of cars and improve fuel efficiency, while still maintaining crash-worthiness.

"By early next century, supercomputer performance is expected to increase to the petaflops level," said Reagan Moore, associate director for enabling technologies for SDSC and co-investigator on the grant. "We will be testing MTA on a small scale to see if it might eventually provide the framework for much more powerful supercomputers."

SDSC, a national laboratory for computational science and engineering, is sponsored by NSF, other federal agencies, the State and University of California, and private organizations; is affiliated with the University of California, San Diego; and is administered by General Atomics. For more information, see http://www.sdsc.edu/ or contact Ann Redelfs, SDSC, redelfs@sdsc.edu, 619-534-5032.

For more information about Tera Computer Company (NASDAQ: TERA), contact the company at 2815 Eastlake Avenue E, Seattle, WA 98102. Phone: (206) 325-0800, Fax: (206) 323-1318, E-mail: info@tera.com or http://www.tera.com.