SDSS IPP Webinar Series





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SDSC Industry Partners Program (IPP)

Webinar Series

Benchmarking the Xeon Phi Processor

Wednesday, May 14, 2014:
11:00 - Noon PST / 2:00 – 3:00 PM EST
David Nadeau, Ph.D.
Computer Scientist, SDSC

***** Cancelled *****

Webinar Abstract

Intel's Xeon Phi processor has 61 x86-compatible cores, vector processing, four threads per core, GDDR5 memory, and 16 memory channels. This combination is off the charts in specs like theoretical peak memory bandwidth and theoretical peak GFLOPS. But what can it really do?
This talk summarizes recent SDSC micro-benchmarking efforts to look at the actual memory bandwidth, cache and memory latency, and GFLOPS of the processor and how all this scales with the number of cores and threads. Along the way we'll talk about problems with current industry standard micro-benchmarks, like STREAM, and how to get more accurate benchmark results.
To provide context, this talk will compare benchmark results for the Xeon Phi with other current generation Xeons.
About the Speaker
David Nadeau is a senior computer scientist specializing in visualization and high-performance computing.  He specializes in very large high-dimensionality data sets for such diverse fields as geoscience, astrophysics, and medical imaging.  His work visualizing nebulae are featured in planetarium shows from the American Museum of Natural History in New York City.  He has taught courses in computer graphics and is the co-author of two books on the subject.